1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device such as an LSI, and particularly to a semiconductor integrated circuit device equipped with a hard macro containing a memory controller.
2. Description of the Related Art
This application is counterpart of Japanese patent application, Serial Number 382212/2003, filed Nov. 12, 2003, the subject matter of which is incorporated herein by reference.
A semiconductor integrated circuit device such as an LSI normally comprises a plurality of functional blocks. Of these functional blocks, the functional blocks high in general versatility are generally libraried in functional block units so that they can be used in various applications. The functional blocks libraried in this manner are called hard macros. As to the hard macro, its placement on the LSI is limited by the size (large-scaled one in particular) and shape (aspect ratio).
FIG. 6 is a configurational diagram of a conventional LSI provided with a hard macro containing a memory controller for controlling (effecting reading/writing on) an external memory.
As shown in the figure, the LSI 100 is provided with a hard macro 120 and an IO pad unit 130. A CPU 140 and a memory controller 150 are placed in the hard macro 120 and interconnected with each other by a system bus 170.
Wirings such as a control bus, an address bus, etc. are provided between the memory controller 150 and the IO pad unit 130 and between the IO pad unit 130 and an external memory 110, and signals or data are transmitted through the wirings. Described specifically, a control signal is transmitted from the memory controller 150 to the memory 110 via the control buses 160 and 180, and address information is transmitted from the memory controller 150 to the memory 110 via the address buses 162, 182. Also output data is transmitted from the memory controller 150 to the memory 110 through the output data bus 164 and the data bus 184, and input data is transmitted from the memory 110 to the memory controller 150 through the data bus 184 and the input data bus 166.
Incidentally, the conventional semiconductor integrated circuit device using the hard macro has been disclosed in various documents (refer to a patent document 1, for example).
Patent Document 1
Japanese Laid Open Patent No. 2001-168201 (see FIG. 3, paragraphs 0051˜0056).
When the hard macro is laid out at a position away from the IO pad unit in the configuration of the conventional LSI, the wiring between the memory controller and the IO pad unit becomes long. Therefore, a delay in signal increases and timing design between the memory controller and the external memory might fall into difficulties (be critical). Thus, when the timing to be provided for the external memory is critical, the hard macro may preferably be disposed near the IO pad unit. Since, however, the placement of the hard macro on the LSI is limited by the size and shape as described above, there might be no other choice but to lay out the hard macro at the position away from the IO pad unit. In such a case, the design of the timing to be provided for the external memory falls into difficulties.
A technique for facilitating the design of the timing to be provided for the external memory is not disclosed at all even in Japanese Unexamined Patent Publication No. 2001-168201 referred to above.